CMOS image sensors can be manufactured by using the same manufacturing process as for typical CMOS integrated circuits, and can be driven by a single power source. Hence, by using the CMOS process, it is possible to provide analog circuits and logic circuits together in the same chip.
Hence, there is a plurality of strong merits such as reduction in the number of peripheral ICs.
The output circuit of a CCD in mainstream use is a single channel (ch) output type which uses a FD amplifier having a floating diffusion (FD) layer.
In contrast, since the CMOS image sensor has the FD amplifier for each pixel, the output circuit thereof in mainstream use is a column-parallel output type in which a single row in the pixel array is selected and the entire row is simultaneously read in the column direction.
It is difficult for the FD amplifier, which is disposed in each pixel, to exhibit a sufficient driving capability, and thus it is necessary to lower the data rate. This is a reason why the parallel processing is advantageous.
There are proposed various pixel signal reading (output) circuits of column-parallel output type CMOS image sensors.
The most advanced one thereof is a pixel signal reading circuit which has an analog-digital converter (hereinafter abbreviated as an ADC) for each column so as to extract pixel signals as digital signals.
Such a CMOS image sensor equipped with column-parallel ADCs is disclosed in, for example, JP-A-2005-278135 or non-patent document “Integrated 800×600 CMOS Image System” (W. Yang et al., ISSCC Digest of Technical Papers, pp. 304-305, February, 1999).
FIG. 1 is a block diagram illustrating an exemplary configuration of a solid-state imaging device (a CMOS image sensor) equipped with column-parallel ADCs.
A solid-state imaging device 1 includes a pixel section 2, a vertical scanning circuit 3, a horizontal transfer scanning circuit 4, and a column processing circuit group 5 formed by an ADC group as shown in FIG. 1.
The solid-state imaging device 1 further includes a digital-analog converter (hereinafter, abbreviated as DAC) 6 and amplifier circuits (S/A) 7.
The pixel section 2 is configured such that, for example, the unit pixels 21, each of which includes a photodiode (a photoelectric conversion device) and an in-pixel amplifier, are arranged in a matrix shape (a shape of rows and columns).
In the column processing circuit group 5, a plurality of columns of column processing circuits 51, each of which forms the ADC in each column, are arranged.
Each column processing circuit (ADC) 51 includes a comparator 51-1 that compares a reference signal RAMP (Vslop), which has a RAMP waveform obtained when the reference signal generated by the DAC 6 is changed in a stepwise manner, with an analog signal Vsl which is obtained from pixels of each row line through a vertical signal line 8.
Each column processing circuit (ADC) 51 further includes a counter latch (memory) 51-2 which counts the comparison time of the comparator 51-1 and retains the count result.
The column processing circuit 51 has an n-bit digital signal conversion function, and is disposed for each of the vertical signal lines (column lines) 8-1 to 8-n, thereby constituting a column-parallel ADC block.
Outputs of respective counter latches (memories) 51-2 are connected to horizontal transfer lines 9 having, for example, a k-bit width.
In addition, there are disposed k amplifier circuits 7 corresponding to the horizontal transfer lines 9.
FIG. 2 is a diagram illustrating a timing chart of the circuit of FIG. 1.
In each column processing circuit (ADC) 51, the comparator 51-1, which is disposed for each column, compares an analog signal (electric potential Vsl), which is read to the vertical signal line 8, with the reference signal RAMP (Vslop) which changes in a stepwise manner.
At this time, until levels of the analog potential Vsl and the reference signal RAMP (Vslop) intersect each other and an output of the comparator 51-1 is inverted, the counter latch 51-2 performs the count, and then the electric potential (the analog signal) Vsl of the vertical signal line 8 is converted into a digital signal (AD converted).
The AD conversion is performed twice through one reading.
In the first conversion, reset levels (P phase) of the unit pixels 21 are read to the vertical signal lines 8 (8-1 to 8-n) and AD conversion is performed.
The P phase of the reset levels includes variations between pixels.
In the second conversion, signals, which are photoelectrically converted by respective unit pixels 21, are read to the vertical signal lines 8 (8-1 to 8-n) (D phase), and AD conversion is performed.
The D phase also includes variations between pixels, and thus the calculation of (D-phase level−P-phase level) is executed, thereby realizing correlated double sampling (CDS).
Signals converted into digital signals are recorded in the counter latches 51-2, sequentially read to the amplifier circuit 7 through the horizontal transfer lines 9 by the horizontal (column) transfer scanning circuit 4, and finally output.
In such a manner, the column-parallel output processing is performed.
In addition, the count processing of the counter latch 51-2 at the P phase is referred to as primary sampling, and the count processing of the counter latch 51-2 at the D phase is referred to as secondary sampling.